1. Technical Field
The present invention relates in general to high frequency digital systems and, in particular, to controlling the flow of information between a producer and a buffer in a high frequency digital system. Still more particularly, the present invention relates to a method and system for controlling the flow of information from a memoriless producer to a buffer in a high frequency digital system.
2. Description of the Related Art
As processor micro-architectures are optimized toward implementations that support higher clock frequencies, the complexity of the work that can be performed within each clock cycle decreases. This phenomenon has a tendency to introduce increased cycle-time latency into mechanisms which control the flow of information between components in the micro-architecture, effectively delaying critical feedback within such mechanisms and eroding the aggregate bandwidth of the information flow.
This bandwidth erosion occurs when the buffering capacity of downstream components approaches full occupancy, such that the fill time of the remaining available capacity approaches the latency of feedback in the information flow control mechanism. In such cases, the information flow control mechanism often must pessimistically assume worst case information flow to avoid exceeding the buffering capacity of the downstream components. Thus, for example, the information flow control mechanism may assume that information is being sent (and stall information flow appropriately based on downstream capacity considerations) whether or not information is actually sent in order to avoid overflowing the downstream buffers.
In many cases, such bandwidth erosion can be averted by increasing the buffering capacity of downstream-components to minimize the likelihood that high utilizations will dictate precautionary stalls. However, an increase in buffering capacity also raises component cost without providing additional benefit beyond a reduction in bandwidth erosion. In other cases, more sophisticated flow protocols can be introduced, which tolerate information loss due to aggressive capacity speculation by incorporating retry mechanisms. However, such mechanisms can greatly increase complexity, thus inhibiting design verification and testability. Moreover, retry protocols also increase the utilization of the upstream component, possibly requiring an increase in its size and cost.
The present invention offers an attractive alternative for addressing the obstacles to efficient information flow that arise in high frequency digital systems that control, monitor, or perform transformations on streaming information.
In accordance with the present invention, an information handling system, such as a microprocessor, includes a producer that outputs packets, a buffer that receives packets from the producer, buffers the packets, and eventually outputs the packets, and a control unit that controls the flow of packets from the producer to the buffer. The control unit receives as inputs a producer output indication indicating that the producer has output a packet to the buffer and a buffer output indication indicating that the buffer has output a packet. Based upon a capacity of the buffer, a number of the producer output indications, a number of buffer output indications, and a number of grant messages output to the producer within a feedback latency of the control unit, the control unit whether the producer can output a packet without packet loss. In response to a determination that the producer can output a packet without packet loss, the control unit outputs a grant message to the producer indicating that the producer is permitted to output a packet.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.